They're STACKING CPUs Now!

In this video, the host explains the concept of die stacking in CPUs, clarifying that this is not about stacking entire CPUs on a motherboard but stacking actual silicon dies within a package to add functionality. The discussion begins by contrasting die stacking in storage with CPUs, noting that Intel and AMD are pursuing different architectures to implement this technology. The segment on Intel introduces Foveros, a 3D stacking approach used in Lakefield that places a base die with support logic beneath a compute die containing the cores, connected by tiny micro bumps that are about half the width of a human hair. The video explains why close die-to-die communication is beneficial, including lower latency and improved power efficiency due to reduced data transfer energy. The AMD angle focuses on widening cache within the CPU package using 3D design, employing through-silicon vias (TSVs) to connect cache layers rather than micro bumps, which AMD claims can enable substantial performance gains. The host highlights the cache advancements, noting that a multi-core setup could reach up to 192 MB of L3 cache across two chiplets, with potential FPS improvements in gaming cited by AMD. The discussion ends with reflections on the future of high-resolution gaming and the possibility of even more integrated and cooler 3D CPU designs, along with a plug for Redux for custom PC builds and a reminder to subscribe for future episodes.

Topics · Technology · Computer Hardware · Semiconductors · Innovation